CVE-2025-0647

Fixed in a distro release EPSS <1%CVSS 7.9

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Published 2026-01-14 · CVE record · OSV

Products: Arm Neoverse N2, Arm Neoverse V3AE, Arm Neoverse V3, Arm Neoverse V2, Arm Cortex-X925, Arm Cortex-X4, Arm Cortex-X3, Arm Cortex-X2, Arm Cortex-A710, Arm C1-Premium, Arm C1-Ultra

Distro releases